Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same and, more particularly, to a three-dimensional (3D) flash memory device and a method of fabricating the same.
In general, semiconductor memory devices for storing data are classified into volatile memory devices and non-volatile memory devices. Whereas data stored in volatile memory devices is lost when its power supply is stopped, non-volatile memory devices are able to retain data irrespective of whether power is supplied thereto.
Therefore, non-volatile memory devices have been widely used in various applications such as mobile phone systems as well as memory cards for storing music and/or video data. Non-volatile memory may also be used in devices where the power supply may be occasionally interrupted, or when low power consumption is required. An example of a non-volatile memory device includes a flash memory device having data capable of being simultaneously erased. The demand of smaller-sized cells is also increasing in the flash memory devices.
Meanwhile, since the integration enhancement of two-dimensional (2D) non-volatile memory devices (in which a single-layered memory device is formed over a semiconductor substrate) is limited, a three-dimensional (3D) non-volatile memory device has been introduced in which memory cells are stacked vertically from the semiconductor substrate.
FIGS. 1A and 1B respectively illustrate a cross-sectional view and a circuit diagram of a conventional semiconductor device.
Referring to FIGS. 1A and 1B, a pipe gate (PG) 13 is formed over a semiconductor substrate 10, a memory cell structure 25 is formed by repeatedly stacking a first insulation film 20 and a word line 23 over the pipe gate (PG) 13, a source selection line (SSL) 30 is formed at one side of an upper portion of the memory cell structure 25, a drain selection line (DSL) 15 is formed at the other side of the upper portion of the memory cell structure 25, and a second insulation film 33 is formed over the drain selection line (DSL) 15 and the source selection line (SSL) 30.
One pair of cell channel holes 41a and 41b is arranged to pass through the memory cell structure 25, the drain selection line (DSL) 15, and the source selection line (SSL) 30. A pipe channel hole 41c for interconnecting the cell channel holes 41a and 41b may be arranged below the memory cell structure 25. An oxide-nitride-oxide (ONO) dielectric layer 39 is formed along inner walls of the cell channel holes 41a and 41b and the pipe channel hole 41c, and a pipe channel region 45 is formed by forming a channel film (not shown) over the ONO dielectric layer 39.
One side of the pipe channel region 45 is coupled to a source line (SL) 40, and the other side of the pipe channel region 45 is coupled to a bit line (BL) 54.
Since a space for interconnecting the source line (SL) 40 to an upper metal line (not shown) is additionally required for the above-mentioned 3D memory cell structure, space utilization deteriorates.
In addition, a pipe-channel-shaped 3D memory cell structure that is configured work with the pipe gate (PG) is highly difficult to fabricate, and therefore requires a complex fabrication process.